Chat with us, powered by LiveChat Digital Electronics Verification of Logic Gates Paper - Uni Pal

DescriptionExperiment No: 1: VERIFICATION OF LOGIC GATES

Aim:
To study and verify the truth table of different logic gates.

Apparatus:
1. Logic gate ICs 7404, 7408, 7432, 7402, 7400, 7486.
2. Connecting wires.

Theory:
A logic gate is an electronic circuit which takes in one or more inputs and produces a single output. The
possible combinations of the inputs and the corresponding outputs are tabulated in a truth table. The
main logic gates are: AND, OR, NOT, NAND, NOR and EX-OR gates which represented by the symbols
below:

Procedure:

– Give the connections as per the circuits given.
– Switch on trainer kit.
– Note down the output for each possible combination of the inputs.
Observations:
Observe, draw and fill the truth table for each gate:
1- AND gate:
2- OR gate:
3- NOT gate:
4- NAND gate:
5- NOR gate:
6- EX-OR:

Conclusion:
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Experiment No:2: VERIFICATION OF DEMORGAN’S THEOREMS

Aim:
To verify the De-Morgan’s theorem.

Apparatus:
1. Logic gate ICs 7432, 7408, 7404.
2. Connecting wires.

Theory:
De-Morgan’s theorem states that, “the complement of a product is equal to sum of the
complements and the complement of a sum is equal to product of the complements”.
(i) A + B = A . B
(ii) A.B = A + B
They are duals of each other. These laws can be expressed as:
a. The individual variables can be removed from under a NOT sign.
b. It allows the transformation from a sum of products form to a product of sums form.
The circuit diagrams for the each expression are following:
A+ B= A.B
A.B = A + B

Procedure:


Give the connections as per the circuits given.
Switch on trainer kit.
Note down the output for each possible combination of the inputs.
Observation:
Observe, draw and fill the truth table for each expression of Demerger’s theorem.
1.
A+ B= A.B
2.
A.B = A + B

Conclusion:
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Experiment No: 3: UNIVERSAL GATES

Aim:
To verify the representation of each digital logic gate using universal gates.

Apparatus:
1. Logic gate ICs 7402, 7400.
2. Connecting wires.

Theory:
The gates NAND and NOR can be used to develop only one of the three basic building blocks. Since
the basic building blocks can be used to realize any Boolean expression, it means that one can use
only NAND gates or only NOR gates to realize any Boolean expression. Hence these two gates are
known as universal building blocks. The manner in which these two gates can be used to develop
the basic building blocks is shown below.
A) NAND gate:
B) NOR gate:

Procedure:


Construct the realization of the NOT, OR & AND gates on the trainer using only NOR gates
Switch on trainer kit.
Verify the truth table for each circuit.
Repeat the procedure using only NAND gates.
Observation:
Observe, draw and fill the truth table for each gate by using NOR gates.

NOT gate:

OR gate:

AND gate:
Observe, draw and fill the truth table for each gate by using NAND gates.

NOT gate:

OR gate:

AND gate

Conclusion:
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Experiment No:4: ADDER AND SUBTRACTOR

Aim:
To verify the truth tables of half-adder, full-adder, half subtractor and full subtractor.

Apparatus:
1. Logic gate ICs 7404, 7408, 7486, 7432.
2. Connecting wires.

Theory:
The basic operations in a digital computer are addition and subtraction, as multiplication is repeated
addition, and division is repeated subtraction. Hence the binary adder and subtractor are important
building blocks in a digital computer. The binary addition is done either serially or paralleled. In serial
addition, the execution time is more and hard ware is less. Depending on the number of bits to be
added the adder can be classified as half-adder or full-adder.
In binary subtraction the outputs consists of difference and borrow. Just like adders half subtractors
and full subtractors are available. The circuit diagrams for half adder, half subtractor, full adder and
full subtractor are shown below:
HALF ADDER
HALF SUBTRACTOR

Procedure:
– Give the connections as per the circuits given.
– Switch on trainer kit.
– Verify the tables for half-adder, full-adder, half-subtractor and full-subtractor.

Observation:
Observe, draw and fill the truth table for each operator.

half-adder:

half-subtracrtor:
Conclusion:
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Experiment No:5: MULTIPLEXER AND DEMULTIPLEXER

Aim:
To study the function of multiplexer and de-multiplexer.

Apparatus:
1. Logic gate IC 74153 and IC 74139.
2. Connecting wires.

Theory:
The multiplexer and the De-multiplexer are two important circuits in digital electronics .The multiplexer
is a special combinational circuit that is one of the most widely used standard circuits in digital design.
The multiplexer is a logic circuit that gates one out of several inputs to a single output. The input
selected is controlled by a set of select inputs. Pin configuration of a multiplexer (IC74153) is shown
below.
De-multiplexers take one data input and a number of selection inputs, and they have several
outputs. They forward the data input to one of the outputs depending on the values of the selection
inputs. It is used when a circuit wishes to send a signal to one of many devices. This description
sounds similar to the description given for a decoder, but a decoder is used to select among many
devices while a de-multiplexer is used to send a signal among many devices. Pin configuration of demultiplexer (IC 74139) is shown below.
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin description
Enable 1G’
Select 1A
Select 1B
o/p 1Y0
o/p 1Y1
o/p 1Y2
o/p 1Y3
GND
o/p 2Y3
o/p 2Y2
o/p 2Y1
o/p 2Y0
Select 2B
Select 2A
Enable 2G’
16

VCC
Procedure:
Multiplexers
1. Connect four input logic level switches to the A0, B0, C0, D0 (orA1, B1, C1, D1) terminals.
2. Connect one input logic level switch to the terminal and two switches to the select A and select
B inputs.
3. Connect Y0 (or Y1) terminal to the LED output terminal.
4. Switch on trainer kit.
5. Verify the truth tables.
De-Multiplexers
1. Connect one input logic level switches to the 1G’ (or 2G’) terminal.
2. Connect two switches to the select 1A and select 1B inputs.
3. Connect 1Y0, 1Y1, 1Y2, 1Y3 (or 2Y0, 2Y1, 2Y2, 2Y3) terminals to the LED output terminals.
4. Switch on trainer kit.
5. Verify the truth tables.

Observation:
Observe, draw and fill the truth table for Multiplexer.
Observe, draw and fill the truth table for de-multiplexer.

Conclusion:
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Observations:
Observe, draw and fill the truth table for each gate:
1- AND gate:
Input A
Input B
Output Y
0
0
0
0
1
0
1
0
0
1
1
1
Input B
Output Y
0
0
0
0
1
1
1
0
1
1
1
1
2- OR gate:
Input A
3- NOT gate:
Input A
Output Y
0
1
1
0
4- NAND gate:
Input A
Input B
Output Y
0
0
1
0
1
1
1
0
1
1
1
0
Input A
Input B
Output Y
0
0
1
5- NOR gate:
0
1
0
1
0
0
1
1
0
Input B
Output Y
0
0
0
0
1
1
1
0
1
1
1
0
6- EX-OR:
Input A

Conclusion:
1. In this experiment is there one or more input.
2. In the AND gate if 0 enter at any input the output will be 0 and in the case of all 1 input the
output will be 1.
3. In the OR of all input o the output is 0 and if any two input 1 the output will be 1.
4.
5.
6.
7.
In the NOT is there one input and one output.
XOR give 0 if all entries are equal.
NOR give 1 if the all entries is 0.
NAND give o if all enters is 1.
Experiment No:2: VERIFICATION OF DEMORGAN’S THEOREMS

Aim:
To verify the De-Morgan’s theorem.

Apparatus:
1. Logic gate ICs 7432, 7408, 7404.
2. Connecting wires.

Theory:
De-Morgan’s theorem states that, “the complement of a product is equal to sum of the
complements and the complement of a sum is equal to product of the complements”.
(i) A + B = A . B
(ii) A.B = A + B
They are duals of each other. These laws can be expressed as:
a. The individual variables can be removed from under a NOT sign.
b. It allows the transformation from a sum of products form to a product of sums form.
The circuit diagrams for the each expression are following:
A+ B= A.B
A.B = A + B

Procedure:

Give the connections as per the circuits given.
Switch on trainer kit.
Note down the output for each possible combination of the inputs.

Observation:
Observe, draw and fill the truth table for each expression of Demerger’s theorem.
1.
A+ B= A.B
Input A
Input B
Output Y
0
0
1
0
1
0
1
0
0
1
1
0
2.
A.B = A + B
Input A
Input B
Output Y
0
0
1
0
1
1
1
0
1
1
1
0

Conclusion:
1. Complement of a product is equal to addition of the complement .
2. Complement of a sum id equal to the product of complement.
Experiment No: 3: UNIVERSAL GATES

Aim:
To verify the representation of each digital logic gate using universal gates.

Apparatus:
1. Logic gate ICs 7402, 7400.
2. Connecting wires.

Theory:
The gates NAND and NOR can be used to develop only one of the three basic building blocks. Since
the basic building blocks can be used to realize any Boolean expression, it means that one can use
only NAND gates or only NOR gates to realize any Boolean expression. Hence these two gates are
known as universal building blocks. The manner in which these two gates can be used to develop
the basic building blocks is shown below.
A) NAND gate:
B) NOR gate:

Procedure:


Construct the realization of the NOT, OR & AND gates on the trainer using only NOR gates
Switch on trainer kit.
Verify the truth table for each circuit.
Repeat the procedure using only NAND gates.
Observation:
Observe, draw and fill the truth table for each gate by using NOR gates.


NOT gate:
A
Y
0
1
1
0
OR gate:
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1

AND gate:
A
B
Y
0
0
0
0
1
0
1
0
0
1
1
1
Observe, draw and fill the truth table for each gate by using NAND gates.


NOT gate:
A
Y
0
1
1
0
OR gate:
A
B
Y
0
0
0
0
1
1
1
0
1
1
1
1

AND gate
A
B
Y
0
0
0
0
1
0
1
0
0
1
1
1

Conclusion:
1. And , or and not are sufficient to implement any digital system.
2. If we can convert nand and nor to these three we can say that any circuit can be implement
nand or nor alone.
Experiment No:4: ADDER AND SUBTRACTOR

Aim:
To verify the truth tables of half-adder, half subtractor.

Apparatus:
1. Logic gate ICs 7404, 7408, 7486, 7432.
2. Connecting wires.

Theory:
In binary subtraction the outputs consists of difference and borrow. Just like adders half subtractors
and full subtractors are available. The circuit diagrams for half adder, half subtractor, full adder and
full subtractor are shown below:
HALF ADDER
HALF SUBTRACTOR

Procedure:
– Give the connections as per the circuits given.
– Switch on trainer kit.
– Verify the tables for half-adder, full-adder, half-subtractor and full-subtractor.

Observation:
Observe, draw and fill the truth table for each operator.

half-adder:
INPUT

OUTPUT
A
B
SUM
CARRY
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
half-subtracrtor:
INPUT
OUTPUT
A
B
DIFF
BORROW
0
0
0
0
0
1
1
1
1
0
1
0
1
1
0
0
Conclusion:
1. The half adder is a basic electronic circuit used to add two binary digital.
2. It will have two output sum and carry.
3. The sum output result of adding two binary together carry output represents the carry by
the addition.
Experiment No:5: MULTIPLEXER AND DEMULTIPLEXER

Aim:
To study the function of multiplexer and de-multiplexer.

Apparatus:
1. Logic gate IC 74153 and IC 74139.
2. Connecting wires.

Theory:
The multiplexer and the De-multiplexer are two important circuits in digital electronics .The multiplexer
is a special combinational circuit that is one of the most widely used standard circuits in digital design.
The multiplexer is a logic circuit that gates one out of several inputs to a single output. The input
selected is controlled by a set of select inputs. Pin configuration of a multiplexer (IC74153) is shown
below.
De-multiplexers take one data input and a number of selection inputs, and they have several
outputs. They forward the data input to one of the outputs depending on the values of the selection
inputs. It is used when a circuit wishes to send a signal to one of many devices. This description
sounds similar to the description given for a decoder, but a decoder is used to select among many
devices while a de-multiplexer is used to send a signal among many devices. Pin configuration of demultiplexer (IC 74139) is shown below.
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin description
Enable 1G’
Select 1A
Select 1B
o/p 1Y0
o/p 1Y1
o/p 1Y2
o/p 1Y3
GND
o/p 2Y3
o/p 2Y2
o/p 2Y1
o/p 2Y0
Select 2B
Select 2A
Enable 2G’
16

VCC
Procedure:
Multiplexers
1. Connect four input logic level switches to the A0, B0, C0, D0 (orA1, B1, C1, D1) terminals.
2. Connect one input logic level switch to the terminal and two switches to the select A and select
B inputs.
3. Connect Y0 (or Y1) terminal to the LED output terminal.
4. Switch on trainer kit.
5. Verify the truth tables.
De-Multiplexers
1. Connect one input logic level switches to the 1G’ (or 2G’) terminal.
2. Connect two switches to the select 1A and select 1B inputs.
3. Connect 1Y0, 1Y1, 1Y2, 1Y3 (or 2Y0, 2Y1, 2Y2, 2Y3) terminals to the LED output terminals.
4. Switch on trainer kit.
5. Verify the truth tables.

Observation:
Observe, draw and fill the truth table for Multiplexer.

A
B
C
D
Out
0
0
0
X
X
X
0
0
0
1
X
X
X
1
0
1
X
0
X
X
0
0
1
X
1
X
X
1
1
0
X
X
0
X
0
1
0
X
X
1
X
1
1
1
X
X
X
0
0
1
1
X
X
X
1
1
Observe, draw and fill the truth table for de-multiplexer.

0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
0
1

Conclusion:
The conclusion for multiplexer:
1. It is combinational circuit that select binary information from one of many input lines and
directs to output line.
2. Reduces number of wires.
3. Reduces circuit complexity cost.
4. Implementation of various circuit using mux.
The conclusion for multiplexer:
1. One input and many output.
2. Reverse operation of multiplexer.
3. One to many data distributer.

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